Thanks for the processor AMD EPYC GENOAIntended for the server, more information has been leaked around AMD’s upcoming microarchitecture, Zen 4, And that at least these processors will support instruction sets AVX3-512 In addition to BFloat16 Y “Other ISA Instructions“.
With the support of AVX-512 instruction it is thus ended on one stroke The only strength of the Intel Xeon processor, Which is always analyzed in benchmarks that leverage the above instructions to increase the performance gains over their competitors. If this leak is correct, then no more slides with handheld benchmarks to show unrealistic gains.
It should be remembered that yesterday it was again indicated that these processors would arrive with the configuration up to 96 cores and 192 processing threads With memory configuration Dodeca(12)-Channel, Which is an extension of the information in this case, indicating that it will basically support RAM memory DDR5 @ 5200 MHz Using socket SP 5 (LGA-6096), maximum reach of 128 lane PCI-Express 5.0 (160 for dual CPU configurations), and will have a top-of-the-range 96-core model A TDP of 320W (cTDP de 400W).
On the other hand, it is indicated that the socket size is 72 x 75.4 mm, and this large increase is associated with an increase in the number of cores in the form of a chiplet design. 12 died (CCD) With 8 cores each.